1. Field of the Invention
The present invention relates to a non-volatile memory device. More particularly, the present invention relates to an erasing method for a non-volatile memory.
2. Description of the Related Art
Non-volatile memory is a type of data storage device capable of retaining data even after power to the device is removed. Therefore, this type of memory has become one of the indispensable components inside many electronic products for initiating a normal start-up operation. In particular, flash memory is a type of non-volatile memory that allows multiple data writing, reading and erasing operations. With these advantages, flash memory has become one of the most widely adopted non-volatile memories for personal computers and electronic equipments.
A typical flash memory has a floating gate and a control gate fabricated using doped polysilicon. Furthermore, the control gate is directly disposed above the floating gate. The floating gate and the control gate are separated from each other through a dielectric layer. The floating gate is also separated from the substrate through a tunneling oxide layer (in the so-called stacked gate flash memory).
At present, the frequently used flash memory array may have a NOR gate array structure or a NAND gate array structure. Because all the memory cells in a NAND gate array structure are serially connected together, it has a higher level of integration than the NOR gate array structure. In general, the erasing operation of the memory cell in a NAND gate array structure includes pulling electrons from the floating gate into the substrate via the tunneling oxide layer. Hence, the tunneling oxide layer can be damaged when operating at a high voltage, thus adversely affecting the reliability of the device.
On the other hand, to prevent data errors due to serious over-erasure of a typical flash memory, an additional select gate is often set up on the sidewalls of the control gate and the floating gate and above the upper surface of the substrate to form a split-gate structure.
To erase data from a NAND gate array structure having select gates, a 0 volt (V) is applied to the control gate and a positive biased voltage is applied to all the select gates. As a result, a large electric field is established between the floating gate and the select gate so that the electrons are pulled out from the floating gate into the select gate. However, the aforementioned erasing method will lower the electric field between the floating gate and the select gate due to a coupling effect between adjacent select gates, which lowers the erasing efficiency of the memory.
Another erasing method is proposed by applying a positive biased voltage to the odd-numbered select gates of the NAND gate array structure and applying a 0V to the even-numbered select gates. Alternatively, a 0V is applied to the odd-numbered select gates of the NAND gate array structure and a positive biased voltage is applied to the even-numbered select gates to complete the data erasing operation. In other words, the foregoing erasing method utilizes just one side of the NAND gate array structure to improve inefficient erasing of the data in the memory. However, this method also has a few problems. For example, erasing failure may appear on the same row of memory cells during the erasing operation, and the reliability and yield of the memory device will be significantly affected.